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Verification Engineer

Listed on: 11/7/2018 12:31:00 PMPST
Location: ,
Industry: Engineering
Salary: Open
Description:  Develop SystemVerilog and UVM verification environments for block-level and top-level modules Build and maintain verification plans Write and run test cases for RTL simulation Debug functional errors in the RTL by working closely with design engineers Define and implement functional coverage and constrained random verification methods Develop and improve design verification environment to ensure coverage closure
Requirements: 1) Experience with SystemVerilog with assertions, UVM test benches 2) Experience with C and C++ and scripting languages 3) Familiarity with industry standard ASIC EDA tools, including logic simulators, debuggers, and linters 4) Compliance with Export Regulations Other Skills Desired, Years in each skill, where applicable: At least 3 year experience in any of the following: SystemVerilog, UVM, SystemC, Verilog or VHDL At least 1 year in C++/Python and Object Oriented Methodology L. J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status.