Design EngineerListed on: 2/12/2019 11:45:00 AMPST
Description: Need for an experienced physical implementation engineer. This engineer will assist in the development, implementation and testing of a digital neuromorphic accelerator chip. The selected candidate will work directly with other designers and system architects to implement ASIC physical design. Job Duties: • Synthesis and placement-driven synthesis • DFT and DFM implementation • Power/Performance/Area estimations • In-depth understanding of memory structures • Physical design, including power grids, clock network implementation, floorplaning, place and route • Simulation and debugging • Timing closure and signoff • Power optimization and signoff • Extensive Scripting / Flow Automation
Requirements: 1) Familiarity with industry standard ASIC EDA tools, including device simulators, synthesis, place and route, timing closure, power integrity, and DFT (with emphasis on Cadence tools). 2) Chip implementation experience. 3) Extensive participation in multiple successful large-scale tapeouts. 3) Compliance with Export Regulations. Other Skills Desired, Years in each skill, where applicable: At least 4 year experience in multiple of the following categories: Place and route, Timing closure, Power optimization, DFT. At least 2 year experience in scripting: Tcl and Python required. L. J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status.