Design EngineerListed on: 6/26/2019 10:55:00 AMPST
Description: RTL/Logic Design Engineer Need for an experienced digital logic design engineer. This engineer will assist in the design, development, and test of a digital neuromorphic accelerator chip. The selected candidate will work directly with other designers and system architects to implement ASIC logic. Job Duties: *RTL coding of circuit, block, and top-level modules *Simulation, logic debugging, and verification *Timing closure *Power optimization *Synthesis and placement-driven synthesis *Scripting
Requirements: 1) Chip design experience with functional and structural SystemVerilog 2) Familiarity with industry standard ASIC EDA tools, including logic simulators, synthesis, timing closure, and power optimization 3) Compliance with Export Regulations At least 3 year experience in any of the following: SystemVerilog, Verilog, or VHDL--including simulation and timing closure At least 1 year in Scripting, Tcl and Python preferred L. J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status.