Computer Engineer

Listed on: 4/2/2020 8:26:00 AMPST
Location: ,
Industry: Engineering
Salary: Open
Description: ASIC Design Engineer -- Verilog Simulation and Top level integration - Electrical / Computer Engineer Need for an experienced and growth minded mission engineer. This engineer will be responsible for Verilog simulation in a Cadence environment. This effort includes the setup, run and debug of Verilog simulations in a Cadence Incisive/Xcelium environment, the ability to read/edit standard Verilog models (ie debug issues), the ability to assemble of chip design modules into a top-level chip and the ability to read/write TLC scripts. Prior experience with ASIC chip design using the Cadence design environment, an intimate knowledge/use of scripting languages such as TCL and preferably, experience with the Avera Semi (now Marvell) FX14 ASICs Dflow, is required. The selected candidate will be required to work both independently and collaboratively in conjunction with other teams. As such, the ability to be a hands-on person is critical, capable of running tools, while working effectively with others, while having the willingness and ability to learn new tools.
Requirements: . Job Duties: Job Duty 1 setup, run, and debug verilog simulations in a Cadence environment (i.e. Incisive/Xcelium). Job Duty 2 - Debug Verilog and integrate Verilog chip components/modules to form a top-level chip. Job Duty 3 - Read/write TCL scripts as needed. Job Duty 4 - Interact with customers (when needed) through technical exchange meetings (TEMs), formal reviews at key program milestones, system demonstrations and briefings, while providing written documentation for the work performed. L. J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status.

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