Design EngineerListed on: 9/15/2020 8:18:00 AMPST
Description: Need for an experienced digital logic design engineer. This engineer will assist in the design, development, and test of a digital neuromorphic accelerator chip. The selected candidate will work directly with other designers and system architects to implement ASIC logic under the supervision of team lead. Task Description: The candidate must be able to perform the following tasks at start date: *RTL coding of circuit, block, and top-level modules *Simulation, logic debugging, and verification *Timing closure *Power optimization *Synthesis and placement-driven synthesis *Scripting
Requirements: Required skills/Level of Experience : *At least 5 years chip design experience with functional and structural SystemVerilog *Proficient at running industry standard ASIC EDA tools, including logic simulators, synthesis, timing closure, and power optimization *Ability to work in an integrated team environment *Ability to design from a high-level specification Nice to have skills: *At least 10 years experience in any of the following: SystemVerilog, Verilog, or VHDL--including simulation and timing closure L. J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status.