Verification Engineer

Listed on: 3/4/2020 11:20:00 AMPST
Location: ,
Industry: Engineering
Salary: Open
Description: Need for an experienced PCIe and AXI logic design and verification expert. This engineer will assist the integration of Cadence PCIe IP in a neuromorphic accelerator chip, from the logic design and verification perspective. The selected candidate will work directly with other designers and system architects under the supervision of team lead. Task Description: Candidates are expected to understand the PCIe and AXI protocol and design/modify/test/verify the integration logic of Cadence PCIe IP into an ASIC design. They are expected to perform all or part of the following tasks: *Create Verilog/SystemVerilog RTL to interface and control a 3rd party PCIe IP through AXI and APB buses. *Integrate a 3rd party PCIe IP (PHY and controllers), its interface logic, PLL, SRAMs into an ASIC chip. *Create a UVM-based test benches and test environments. *Simulate and test the integrated PCIe design. *Examine failed simulations and waveforms and fix the functional bugs in the RTL. *Collaborate with logic design, verification, and physical design team members in a dynamic environment. IBM’s brain-inspired computing group, with a U.S Government Customer, has a need for an experienced PCIe and AXI logic design and verification expert. This engineer will assist the integration of Cadence PCIe IP in a neuromorphic accelerator chip, from the logic design and verification perspective. The selected candidate will work directly with other designers and system architects under the supervision of IBM’s team lead. Task Description: Candidates are expected to understand the PCIe and AXI protocol and design/modify/test/verify the integration logic of Cadence PCIe IP into an ASIC design. They are expected to perform all or part of the following tasks: *Create Verilog/SystemVerilog RTL to interface and control a 3rd party PCIe IP through AXI and APB buses. *Integrate a 3rd party PCIe IP (PHY and controllers), its interface logic, PLL, SRAMs into an ASIC chip. *Create a UVM-based test benches and test environments. *Simulate and test the integrated PCIe design. *Examine failed simulations and waveforms and fix the functional bugs in the RTL. *Collaborate with logic design, verification, and physical design team members in a dynamic environment.
Requirements:  Required Expertise: *Good understanding of PCIe and AXI protocol; *Ability to run tests on a third party PCIe IP and its surrounding logic, and understand the waveforms; *Experience with Verilog/SystemVerilog logic design and verification; *Familiarity with linux environment; *Familiarity with industry standard ASIC EDA tools, including logic simulators and debuggers; *Familiarity with UVM-based verification environment if the candidate works on the verification side. Ideal candidates will have additional expertise in all of the following areas: *Experience in integrating a 3rd party PCIe IP into an ASIC chip; *Experience in APB bus protocol; *Experience in DMA engines; *Experience in PCIe linux driver and application programs; *Understanding of PCIe power management and power states; *At least 3 year experience in Verilog, SystemVerilog, and UVM; *Familiarity on Cadence EDA tools, including their simulators and debuggers; *Ability to create and debug SystemVerilog and UVM for verification. Additional Preferred Skills: *Experience with DFT; *Understanding of SRAM memory types and integration; *Experience with JTAG; *Experience with ASIC chip designs with multiple-clock domains; *Basic machine learning and neural hardware knowledge. L. J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status.

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