Design Engineer

Listed on: 7/1/2021 5:48:00 AMPST
Location: ,
Industry: Engineering
Salary: Open
Description: Need for a very experienced and growth minded mission engineer. This engineer will be responsible for System Verilog verification in a Cadence environment. This effort will primarily focus on the writing of tests for individual components of the chip in a progressive sequence based on the functional description provided in the chip specification Workscope includes test creation, setup, run and debug of Verilog simulations in a Cadence Incisive/Xcelium environment, the ability to read/edit standard Verilog models (ie debug issues), the ability to assemble of chip design modules into a top-level chip and the ability to read/write TLC scripts. Prior experience with ASIC chip design using the Cadence design environment, an intimate knowledge/use of scripting languages such as TCL.
Requirements: Task Description: Job Duty 1 Write/code verification tests based on the chip specification. Job Duty 2 Setup, run, and debug verilog simulations in a Cadence environment (i.e. Incisive/Xcelium).Job Duty 3 Debug Verilog Required skills/Level of Experience : ASIC Design Engineer -- Verilog Simulation - Electrical / Computer EngineerAt least 10-15 years of experience. Experience with assembly language coding, writing in C and with the debugging of complex processor logic is essential. L. J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status.

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