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Verification Engineer

Listed on: 3/6/2019PST
Location: , Ca
Industry: Engineering
Salary: Open
Description: Need for an experienced verification engineer. This engineer will assist in the design, development, Basic Skills, clearances and other elements required, in order of importance, and number of years experience, where applicable, in each skill: 1) Experience with SystemVerilog with assertions, UVM test benches 2) Experience with C and C++ and scripting languages 3) Experience with linux environment 4) Familiarity with industry standard ASIC EDA tools, including logic simulators, and debuggers 5) Familiarity with formal verification and linters 6) Compliance with Export Regulations
Requirements:  1) Experience with SystemVerilog with assertions, UVM test benches 2) Experience with C and C++ and scripting languages 3) Experience with linux environment 4) Familiarity with industry standard ASIC EDA tools, including logic simulators, and debuggers 5) Familiarity with formal verification and linters 6) Compliance with Export Regulations Other Skills Desired, Years in each skill, where applicable: At least 3 year experience in any of the following: SystemVerilog, UVM, SystemC, Verilog or VHDL At least 1 year in C++/Python and Object Oriented Methodology L. J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status.