Design Engineer

Listed on: 8/20/2019PST
Location: ,
Industry: Engineering
Salary: Open
Description: *RTL coding of circuit, block, and top-level modules *Simulation, logic debugging, and verification *Timing closure *Power optimization *Synthesis and placement-driven synthesis *Scripting
Requirements: 1) Chip design experience with functional and structural SystemVerilog 2) Familiarity with industry standard ASIC EDA tools, including logic simulators, synthesis, timing closure, and power optimization 3) Compliance with Export Regulations Other Skills Desired: At least 3 year experience in any of the following: SystemVerilog, Verilog, or VHDL--including simulation and timing closure At least 1 year in Scripting, Tcl and Python preferred L. J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status.

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