Electrical/Electronic EngineerListed on: 11/7/2018 12:25:00 PMPST
Description: *Physical design, including place and route *Timing closure and signoff *Power optimization and signoff *Synthesis and placement-driven synthesis *RTL coding of circuit, block, and top-level modules *Simulation, logic debugging, and verification *Scripting
Requirements: 1) Familiarity with industry standard ASIC EDA tools, including logic simulators, synthesis, place and route, timing closure, power integrity, and DFT 2) Chip design experience with functional and structural SystemVerilog 3) Compliance with Export Regulations Other Skills Desired, Years in each skill, where applicable: At least 3 year experience in any of the following: Place and route, Timing closure, SystemVerilog, Verilog, or VHDL. At least 1 year in Scripting, Tcl and Python preferred L. J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status.