Design EngineerListed on: 11/22/2019 12:35:00 PMPST
Description: Need for an experienced physical implementation engineer. This engineer will assist in the development, implementation and testing of a digital neuromorphic accelerator chip. The selected candidate will work directly with logic designers and system architects to implement ASIC physical design under the supervision team lead. Task Description: Candidates are expected to create/modify/script Physical Design tool flows; as well as perform synthesis, clock tree creation, physical design, timing closure, power/performance/area optimizations and signoff based on the given RTL. L.J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status. L.J. Gonzer Associates is committed to diversity and inclusion in its recruitment process and work place environment.
Requirements: Required skills/Level of Experience: *Hierarchical Chip-level Clock Tree architect (specific additional requirements: advanced scripting in TCL; 5+ years of experience with Cadence Innovus CTS) And/or *Chip-level Timing Closure expert (specific additional requirements: advanced scripting in TCL; 5+ of experience with Cadence Genus, Innovus, Tempus) And/or *Gate-level Simulations Required Expertise: *Multiple successful tapeouts at lower-node technologies (using FinFETs at 14nm nodes and/or below) *At least 4 years experience with Cadence tools in the areas of physical design, including synthesis, LEC, floorplanning, hierarchical clock-tree creation, Place and Route, power grid creation, hierarchical integration, DFM, Signoff *Experience with 3rd party IP-s, integration of IP into the design and IP testing *Ability to perform and understand results of STA, timing closure and timing signoff *Extensive experience with power analysis, power optimizations and power signoff *At least 3 years TCL and SHELL scripting Ideal candidates will have additional expertise in all of the following areas: *Extensive experience with Cadence EDA tools, tool administration, and flow automation *In-depth understanding of memory structures, memory testing and integration *Synthesis (including PLE) and formal equivalence checking *Power/Performance/Area analysis and optimizations *RTL, gate-level and transistor-level simulations and debugging *Ability to create and debug SystemVerilog and UVM *Basic machine learning and neural hardware knowledge *FPGA programming and debugging preferred L. J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status.