Physical DesignerListed on: 10/19/2020 6:56:00 AMPST
Description: Need for an experienced sign-off expert with in-depth understanding of FINFET process nodes, using Cadence Design Suite. This physical design engineer will assist in the development, implementation and testing of a digital neuromorphic accelerator chip. The selected candidate will work with other logic designers and system architects to implement ASIC physical design under the supervision of team lead. Task Description: Candidates are expected to be experts in the Sign-off area (DRC/LVS/Extraction/Simulation) of the ASIC Physical Design using Cadence Design Tools on GlobalFoundries 14nm/12nm process or similar. Candidates must be comfortable in creating scripts using various scripting languages.
Requirements: Required skills/Level of Experience: Position: *Senior Physical Design Engineer. Required Expertise: *Multiple successful tapeouts at lower-node technologies (using FinFETs at 14nm nodes and/or below) *Prior experience and understanding of GF 12LP/14LPP process or similar (rules, settings, techfiles) *· At least 6 years experience with Cadence tools (must know Innovus, Virtuoso, Genus) *Sign-off expertise in DRC/LVS/PEX using Cadence tools *At least 3 years TCL and SHELL scripting Ideal candidates will have additional expertise in all of the following areas: *Extensive experience with multiple Cadence EDA tools, tool administration, and flow automation; *Synthesis (including PLE) and formal equivalence checking; *RTL, gate-level and transistor-level simulations and debugging. Additional Preferred Skills: *3 years of Python/Perl scripting. . L. J. Gonzer Associates is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, or protected Veteran status.